Reduced-width low-error multiplier

ABSTRACT

This invention purposes a reduced-width low-error multiplier that can be used in the DSP (Digital Signal Processing) approach of digital communication system. We derive a binary compensation vector to compensate the error caused by the reduction of area without any hardware overhead. We also implement the compensation structure in Array and Booth multiplier to reduce hardware complexity.

FIELD OF THE INVENTION

[0001] This invention reveals a reduced-width multiplier that has smallerrors. It can be used in processing digital signals of a communicationsystem usch as timing recovery circuit, carrier recovery circuit and FIRfilter.

BACKGROUND OF THE INVENTION

[0002] In the face of the recent fast progress in communication,computation methods have become more complicated. The demand formultipliers is escalating, and efficient multiplier design is deemedimportant. A currently important topic is how to design a multipliercharacterized by low power and area-saving, while meeting therequirements of the integrated circuit design and its applications.

[0003] The operation of a multiplier is basically the expansion of amultiplicand (104), according to the value of a multiplicator (100),resulting in a parallelogram as shown in FIG. 1. The constructioninvolves several steps. Expand a multiplicand (104) in accordance with amultiplicator (100), arrange them by positional weight, and finally addup all the values found in the summation row to produce a product (105).The summation row includes two parts, i.e. the sum of low bits (LP,101), and the sum of high bits (MP, 102). If a multiplicand X has a bitlength of m, and a multiplicator Y has a bit length of n, then theproduct PD will have (m+n) bits. As regards the application of digitalcommunication, the bit number (m+n−p) required by a product is notnecessarily (m+n), but some where in between max(m,n) and (m+n), dependson area, computation speed and performance required by the system, suchas signal-to-noise ratio (SNR), bit error ratio (BER), etc. In general,we take the first (m+n−p) bits which are the most significant bits. Asillustrated in FIG. 1, we take p=n. Error arises between the value weget by taking (m+n−p) bits and the value resulted from taking (m+n)bits.

[0004] Therefore, this invention is to solve a problem, that is, how tosave area while reduce error? As far as the (m+n−p) bits we need, thisinvention uses the first (m+n−p) bits while assigning 0 directly to thelower P bits without any computation, when it comes to Integerfixed-point; or it simply takes the first (m+n−p) bits generated by thisinvention, when Fractional fixed-point is involved.

DESCRIPTION OF THE PRIOR ART

[0005] Amongst existing integrated circuit designs, Array and Boothmultipliers are commonly used when it comes to fast computation. Asregards signal processing in digital communication, the bit length of aproduct term is reduced and determined in response to the SNR requiredby the system. When the bit number of the product is decreased, thecomputation required is also reduced. At present, there are four typesof technology in this regard. FIGS. 2 to 5 illustrate the four methods,using an example of 5×5 with product of six bit integers (m=n=5, p=4).

[0006]FIG. 2 illustrates method 1 said Rounded Method. Calculation isdone on all product terms (202) up to (m+n) bits. After that, theresults between the PD_((m+n−1)) bits and the PD_(p) bits are reserved.This is also known as Truncated Method. An alternative is to round offthe PD_((p−1)) term of the result, and add it to the preceding term, andis then called Rounded Method. This method is generally adopted by mostsystems. Complete computation followed by truncation will yield aresult, and the error between the result and the original product willbe smaller. However, truncating a great amount of product terms whichhave undergone all the computation, means not only a waste ofcomputation time, but also a waste of the hardware area of computation.

[0007]FIG. 3 illustrates method 2 said involves truncation followed bycomputation. Unlike method 1, this method involves truncating the bitnumber of a multiplicand and a multiplicator, so as to conform with therequirement of the system regarding the bit number of product (302).After truncation, the multiplicand and the multiplicator will undergocomputation in a traditional multiplier. For example, if both themultiplicator (100) and the multiplicand (104) consists of five bitsrespectively, while the system requires six bits, they will be truncatedto three bits respectively. In other words, a 5×5 multiplier is reducedto a 3×3 multiplier, in order to decrease the area. The drawback of thismethod is that, the bits of a multiplicator and a multiplicand aretruncated before computation, leading to the removal of thosemultiplicators or multiplicands located in relatively higher weightingpositions, such as X1Y4, X4Y1 . . . (301) and therefore yielding a greaterror.

[0008]FIG. 4 illustrates method 3 said involves compensation with afixed value. In view of the error derived from truncating operationunits of relatively low bits, the product is compensated with a fixedvalue. In this computation, the value to be removed is always foundbehind the bit of the product term to be removed. The fixed value ofcompensation is a result of the statistics conducted on the bit numberof multiplicator (100)s and multiplicand (104)s. Good examples of thiskind are found in the content of U.S. Pat. No. 4,598,382 and Kidambi, S.S. et al. (IEEE Transactions on Circuits and Systems II, Vol. 43, No. 2,pp. 90˜95, 1996). Its underlying theory is that, a certain bit lengthalways yields a certain error, hence it figures out a product (403) byadding in a fixed value. The example in FIG. 4 uses a fixed compensationvalue (402) of 1. The error produced in this method is smaller than thatin method 2, which involves truncation prior to compensation. Thismethod also reduces computation and hardware area. However, due to afixed compensation value that is independent of the multiplicand ormultiplicator is added to the product, the error may still be large. Forinstance, if both the multiplicator and the multiplicand are 0, then theproduct shall be zero. However, this method will still compensate theproduct with a fixed value. Thus, although the average error of thismethod will be smaller than that produced by truncation followed bycomputation, but considerable errors still exist in the product for somecases.

[0009]FIG. 5 illustrates method 4 said involves compensation with anadaptive value. Jou, J. M. et al. (IEEE Transactions on Circuits andSystems II, Vol. 46, No. 6, pp. 836˜842, 1999) figured out acompensation method that the value added to the product term depends onthe distribution of the input signals of the multiplicator (100) and themultiplicand (104). This method yields an average error or an individualerror much smaller than that of method 3 (compensation of fixed value).Nevertheless, Jou, J. M. et al. did not completely take into account ofthe distribution of input signals and the distribution of the intendedcompensation, leading to the surplus of hardware area in thecompensating circuit as well as unnecessary power consumption.

[0010] This invention keeps all the merits of the above circuits andcreates an innovative compensating circuit. It reduces not only powerconsumption due to the reduction of computation and hardware, but alsogenerates a post-compensation product with error smaller than that foundin the design of Jou, J. M. et al.

SUMMARY OF THE INVENTION

[0011] This invention reveals a reduced-width low-error multiplier thatgenerates small errors and allows reduction of bit length. It can beused in processing digital signals of a communication system, resultingin a great decrease in the complexity of the circuit of a multiplier.

[0012] This invention also reveals a kind of innovative compensationvector signal, for compensating the errors made as a result of savingarea. It applies the idea to Array and Booth multiplier, and reveals ahardware structure that is more area-saving.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Table 1: The coding method of Booth multiplier

[0014] Table 2: The probability distribution of α_(n−1)=β−1, β or β+1,with different bit numbers (n)

[0015] Table 3: Evaluation of performance of Array multiplier

[0016] Table 4: Evaluation of performance of Booth multiplier

[0017]FIG. 1: Operation of multiplication

[0018]FIG. 2: Diagrammatic illustration of method 1

[0019]FIG. 3: Diagrammatic illustration of method 2

[0020]FIG. 4: Diagrammatic illustration of method 3.

[0021]FIG. 5: Diagrammatic illustration of method 4.

[0022]FIG. 6: Diagrammatic illustration of the operation ofreduced-width multiplier in this invention

[0023]FIG. 7: P1(x_(I)y_(j)) and the regression curve taken, when n=8

[0024]FIG. 8: The acquired Array multiplier of 5×5 to 5

[0025]FIG. 9: The reduced-width Array multiplier and its compensationcircuit in this invention (5×5→5)

[0026]FIG. 10: J. M. Jou Array multiplier and its compensation circuit(5×5 to 5)

[0027]FIG. 11: An example of reduced-width Array multiplier with 8×8 to10

[0028]FIG. 12: Diagrammatic illustration of the Booth multiplication of8×8 to 16 of the two's complement system.

[0029]FIG. 13: Summand operation of the acquired Booth multiplication of8×8 to 8

[0030]FIG. 14: Diagrammatic illustration of reduced-width Boothmultiplication operation and its compensation terms in 8×8 to 8

[0031]FIG. 15: The method of operation of summand when the bit number isn+1

[0032]FIG. 16: An example of the circuit of the summand row processingunit of the reduced-width Booth multiplier

[0033]FIG. 17: An example of the circuit of the summand processing unitof the Booth multiplier of n+1 bits

REFERENCE NUMBER OF THE ATTACHED DRAWINGS

[0034]100 . . . multiplicator(100)

[0035]101 . . . the summand of low bits (LP)

[0036]102 . . . the summand of high bits (MP)

[0037]104 . . . multiplicand (104)

[0038]105 . . . product (105)

[0039]202 . . . the product arises from method 1

[0040]301 . . . the operation removed

[0041]401 . . . the operand of low bits to be removed

[0042]402 . . . fixed compensation

[0043]501 . . . the compensation number relevant to a removed portion

[0044]601 . . . the removed portion of lower part of summand

[0045]603 . . . the product of a reduced-width, lower-errormultiplication

[0046]604 . . . the reserved portion of higher part of summand

[0047]701 . . . Full-Adder (FA)

[0048]702 . . . Half-Adder (HA)

[0049]703 . . . the proposed compensation terms and circuit forminimizing error

[0050]704 . . . the AND-OR(AO) gate used in method 4

[0051]705 . . . the AND used in method 4

[0052]801 . . . the value of a complete product

[0053]802 . . . the product acquired by method 1

[0054]806 . . . the product acquired by this invention

[0055]901 . . . coder

[0056]902 . . . scaler

[0057]903 . . . the operation of the summand

[0058]904 . . . the compensation number relevant to the removed part.

[0059]1001 . . . the portion of lower bits intended for removal

[0060]1002 . . . summand row with non-truncated operation and higherbits

[0061]1003 . . . compensation number relevant to the removed part

DETAILED DESCRIPTION OF THE INVENTION

[0062] This invention Reduced-Width Low-Error Multiplier reveals a kindof multiplication operation and basic structure that yields small errorsand permits reduction of product terms. It can be applied to the designof multipliers for processing digital signals of a communication system.

[0063] If a multiplicand X (104), has a bit length of m and is denotedby X_(m-1) . . . X_(i) . . . X0, and a multiplicator Y (100), has a bitlength of n and is denoted by Y_(n−1) . . . Y_(j) . . . Y0, then theproduct PD (105) , will have (m+n) bits and is denoted by PD_(m+n−1) . .. PD_(n) . . . PD₀ where i is the ith bit of a multiplicand X and j isthe jth bit of a multiplicator Y.

[0064] As regards a reduced-width multiplier operation, as illustratedin FIG. 6, a multiplicand X (104), has a bit length of m, and amultiplicator Y (100), has a bit length of n, and the product term PD(105), needs a bit number of (m+n−p) where p is the bit length of theproduct term to be removed. This invention will remove the operationthat involves the bit number less than required, such as the lowerportion (LP, 601) of the summand as indicated in FIG. 6. In the exampleof FIG. 6, we take p=n. This invention makes proper compensation inaccordance with the values of a multiplicator (100) and a multiplicand(104). The compensation signal (602) is β, which is the sum ofx_(i)y_(j), when i+j=p−1.$\beta = {{\sum\limits_{{i + j} = {p - 1}}{x_{i}y_{j}}} = {{x_{p - 1}y_{0}} + {x_{p - 2}y_{1}} + \ldots \quad + {x_{1}y_{p - 2}} + {x_{0}y_{p - 1}}}}$

[0065] Add the value of β to the vertical column found at the end of theright-hand side of the higher part of summand (604). The consequence ofthe addition is the formation of a multiplication operation that yieldsa reduced-width multiplier with small error. This new reduced-widthlow-error error multiplier has the following merits:

[0066] 1. It directly eliminates the operation of the least significantbits of product (601), so that less hardware will be required for thecomputation, and the computation will be faster.

[0067] 2. The amplitude of the compensation signals (602) of the errorsvaries with the multiplicator and multiplicand.

[0068] 3. The number (P) of product terms to be reduced may vary, and itrequires no new structural design.

[0069] The multiplication operation method designed by this inventioncan be applied to Array multipliers and Booth multipliers, as well asall the operation methods compatible with this invention, so that itgives rise to a structure providing feasible functions of the sameeffect.

[0070]FIGS. 9 and 14 illustrates how reduced-width low-errormultiplication is applied to Array and Booth multiplier respectively.FIG. 8 shows an conventional Array multiplier of 5×5 to 5 which includesFull-Adder (FA, 701), Half-Adder (HA, 702) array and AND gate.Full-Adder takes three input bits of the same weight ad generates a sumand carry bits. Half-Adder takes two input bits of the same weight adgenerates a sum and carry bits. AND gates are used to generatex_(i)y_(j). Full-Adder (FA, 701) and Half-Adder (HA, 702) array worktogether to add up the values of the summand. In FIG. 8, the dotted lineindicates the operation that will be removed by this invention.

[0071]FIG. 9 illustrates the circuits characterized by reduced-widthlow-error array multiplier of this invention. The circuit includesFull-Adder (701), AND gate and a compensating circuit (703). Thecompensation signal is β, which is the sum of x_(i)y_(j) when i+j=p−1.$\beta = {{\sum\limits_{{i + j} = {p - 1}}{x_{i}y_{j}}} = {{x_{p - 1}y_{0}} + {x_{p - 2}y_{1}} + \ldots \quad + {x_{1}y_{p - 2}} + {x_{0}y_{p - 1}}}}$

[0072] A new array structure to implement the reduced-width low-errormultiplier can be created by adding these compensation vectors to one ofthe Full-Adder that located in the rightmost column. In FIG. 9, the bitsoutlined by the dotted line (703) is a compensation vector introduced bythis invention. These bits have weight like that of P4 and equalsx₄y₀+x₃y₁+x₂y₂+x₁y₃+x₀y₄. The distinguishing features of the inventionare that it does not require any other circuit, but only needs to addthe value of β directly to one of the existing Full-Adder.

[0073] A generally acquired Booth multiplier includes Booth Coder (901),a scaler (902) and summand processing unit. FIG. 12 shows a 8×8 to 16Booth multiplier. In order to speed up operation and decrease the numberrow in summand, every three multiplicator bits (Y_(j+1), Y_(j), Y_(j−1))are grouped as an unit to generate an addition row. The two successiveunits will overlap one bit. Table 1 shows the rule of groupingmultiplicator bits. A multiplication by two is done by moving all thedata leftward by one bit. Coder does the coding operation. Shifting andcomplement operations are done by scaler. In Booth multiplier, thenumber of row in summand can be reduced by 50% due to the codingoperation. Take 8×8 to 16 as an example, it decodes a multiplicand (8bits) according to a multiplicator (8 bits) and gets four rows (903);each row is different from the previous row in the way that the data ofthe former is moved leftward by two bits with respect to that of thelatter. Users can acquire these four rows with whatever circuit theyconsider suitable, though the choice usually depends on the requiredoperation speed.

[0074] This invention reduced-width low-error Booth multiplier includesBooth coders, scalers, Full-Adder and Half-Adder array, and compensatingcircuit. It is characterized by the coding of Booth coders and theshifting and complement operation with a scaler. The coding reduces thenumber of summand by 50%. Full-Adder takes three input bits of the sameweight and generates a sum and carry bits. Half-Adder takes two inputbits of the same weight ad generates a sum and carry bits. Thecompensation signal is β, which is the bit of the (p−1)th verticalcolumn of the original summand. Full-Adder and Half-Adder array worktogether to add up the values of the summand. β is added to the verticalcolumn found at the end of the right-hand side of the reserved summand.

[0075]FIG. 14 illustrates an example about the summand processing unitof the reduced-width, low-error Booth multiplier with 8×8 to 8. Thisinvention will remove the operation that involves bit number less thanrequired (1001) as shown in FIG. 13. However, this invention makesproper compensation in accordance with the values of the multiplicatorand the multiplicand. The compensation signal is β, which is

β=S₁ _(—) ₇ +S ₂ _(—) ₅ +S ₃ _(—) ₃ +S ₄ _(—) ₁

[0076] β is added directly to the vertical column at the end of theright hand side of the reserved summand. Then the summation of the valueof β and the reserved portion of the high part of the summand (1002)form the multiplication operation that yields small error and allows thereduction of bit length.

[0077] The summand processing unit of the of this reduced-width 8×8 to 8Booth multiplier works like the Array multiplier does, that is, itincludes Full-Adder (FA, 701) and Half-Adder (HA, 702) array, andcompensating circuit (1003). The overall circuit is illustrated in FIG.16. Full-Adder takes three input bits of the same weight and generates asum and carry bits. Half-Adder takes two input bits of the same weightand generates a sum and carry bits. Full-Adder (FA, 701) and Half-Adder(HA, 702) array work together to add up the values of the summand. InFIG. 16, the bit outlined (1003) by the dotted line is the compensationvector introduced by this invention. Its original positional weight is

β=S ₁ _(—) ₇ +S ₂ _(—) ₅ +S ₃ _(—) ₃ +S ₄ _(—) ₁.

[0078] β is added to one of the inputs of Full-Adders that are locatedin the rightmost column. The merit of this structure is that, no extracircuits are required to implement the compensation signal. This is oneof the features of this invention.

Technical Content and Characteristics

[0079] Equation 1 below represents the formula of a general multiplier.In equation 1, X denotes a multiplicand (104), Y a multiplicator (100)and PD a product term (105). $\begin{matrix}{{PD} = {{XY} = {{\sum\limits_{i = 0}^{m + n - 1}{{PD}_{i}2^{i}}} = {\left( {\sum\limits_{i = 0}^{m - 1}{X_{i}2^{i}}} \right)\quad \left( {\sum\limits_{i = 0}^{n - 1}{Y_{i}2^{i}}} \right)}}}} & \text{(Equation~~1)}\end{matrix}$

[0080] In this invention, the result of a product is divided into twoparts, i.e. the sum of high bits (MP,102) and the sum of low bits(LP,101), while p denotes the number of bit that is to be truncated inthe final product (105). Hence, equation 1 can be re-written as equation2 and the operations are shown in FIG. 1. In FIG. 1, it is assumed thatp is equal to the number (n) of multiplicands. $\begin{matrix}{{PD} = {{{MP} + {LP}} = {{\sum\limits_{i = p}^{m + n - 1}{{PD}_{i}2^{i}}} + {\sum\limits_{i = 0}^{p - 1}{{PD}_{i}2^{i}}}}}} & \text{(equation~~2)}\end{matrix}$

[0081] In this invention, it is intended that the operation of thesummand of low bits (LP,101) should be removed, and the operation of thesummand of high bits (MP,102) remain intact. However, the removal of thesummand of low bits (LP) operation will lead to a result quite differentfrom the real product (105) value. By deduction, it is found that thecarry from the summand of low bits (LP) to the sum of high bits (MP) isα_(p−1). Therefore, we need a compensation amounts which equals α_(p−1).According to FIG. 1, $\begin{matrix}{\alpha_{p - 1} = \left\lfloor \begin{matrix}{{\frac{1}{2}\left( {{x_{p - 1}y_{0}} + {x_{p - 2}y_{1}} + \ldots \quad + {x_{0}y_{p - 1}}} \right)} +} \\{{\frac{1}{4}\left( {{x_{p - 2}y_{0}} + \ldots \quad + {x_{0}y_{p - 2}}} \right)} +} \\{{\frac{1}{8}\left( {{x_{p - 3}y_{0}} + \ldots \quad + {x_{0}y_{p - 3}}} \right)} + \ldots \quad + {\frac{1}{2^{p - 1}}\left( {{x_{1}y_{0}} + {x_{0}y_{1}}} \right)}}\end{matrix} \right\rfloor} & \text{(equation~~3)}\end{matrix}$

[0082] if we define β as the sum of x_(i)y_(j) when i+j=p−1, then$\beta = {{\sum\limits_{{i + j} = {p - 1}}{x_{i}y_{j}}} = {{x_{p - 1}y_{0}} + {x_{p - 2}y_{1}} + \ldots \quad + {x_{1}y_{p - 2}} + {x_{0}y_{p - 1}}}}$

[0083] We get equation 4, by dividing the value of α_(p−1) into twoparts, i.e. β and the remaining portion (λ). $\begin{matrix}{\alpha_{p - 1} = {\left\lfloor \begin{matrix}{{\frac{1}{2}\left( {{x_{p - 1}y_{0}} + \ldots \quad + {x_{0}y_{p - 1}}} \right)} +} \\{{\frac{1}{4}\left( {{x_{p - 2}y_{0}} + \ldots \quad + {x_{0}y_{p - 2}}} \right)} +} \\{\frac{1}{2^{p - 1}}\left( {{x_{1}y_{0}} + {x_{0}y_{1}}} \right)}\end{matrix} \right\rfloor = \left\lfloor {{\frac{1}{2}\beta} + \lambda} \right\rfloor}} & \text{(equation~~4)}\end{matrix}$

[0084] Jou, J. M. et al. reported a equation of fixed-width method ofm=n=p. However, no restriction (i.e. m=n=p) is imposed on the m, n, p ofequations 1˜4.

[0085] Given a fixed β value, the number of 1 in the multiplicator orthe multiplicand is as follows:

[0086] 2β: C(_(β) ^(n))*C(₀ ^(n-β))*2⁰

[0087] 2β+1: C(_(β) ^(n))*C(₁ ^(n-β))*2¹

[0088] 2β+2: C(_(β) ^(n))*C(₂ ^(n-β))*2²

[0089] 2β+(n−β): C(_(β) ^(n))*C(_(n-β) ^(n−β)*)2^((n-β))

[0090] Given a fixed β value, the maximum number of bits equal to 1amongst the bits of a multiplicator (X, 100) or a multiplicand (Y,104),falls between 2β and (n+β). However, the distribution probabilitybetween 2β and (n+β) is not uniform.

[0091] Take m=n=p as an example, and also define that, the probabilityof yielding a product of 1 after the multiplication of x_(i)y_(j) (theproduct of one bit of a multiplicator and one bit of a multiplicand) isP1(x_(i)y_(j)). $\begin{matrix}{{{P!}\left( {x_{i}y_{j}} \right)} = \left\lbrack \frac{\sum\limits_{i = 0}^{({n - \beta})}\left( {{{i!}\overset{2^{i}}{\left( {n - \beta - i} \right)!}}{\cdot \left( {{2\beta} + i} \right)}} \right)}{{\left( {\sum\limits_{i = 0}^{({n - \beta})}{{i!}\overset{2^{i}}{\left( {n - \beta - i} \right)!}}} \right) \cdot 2}n} \right\rbrack^{2}} & \text{(equation~~5)}\end{matrix}$

[0092] In this invention, we employ regression Line analytical method.Take n=8 as an example, the P1(x_(i)y_(j)) and regression curves areshown in FIG. 7. When n=8, 16, 32 & 64, the value of β/n+0.0712 will bethe nearest curve to P1(x_(i)y_(j)). If P1(x_(i)y_(j)) is approximatedas β/n+0.0712, then we can deduce that λ is $\begin{matrix}\left. {\lambda = {{\left( {\begin{matrix}\beta \\n\end{matrix} + 0.0712} \right)*\left( {\begin{matrix}n \\2\end{matrix} - 1} \right)} = {\begin{matrix}\beta \\2\end{matrix} + {0.03556n} - \begin{matrix}\beta \\n\end{matrix} - 0.07112}}} \right) & \text{(equation~~6)}\end{matrix}$

[0093] The operation described in equation 4 is to directly truncate theproduct terms., If, in this invention, improvement is made by roundingoff the product term, then α_(p−1) will be expressed in a completely newway as shown in equation 7. $\begin{matrix}\begin{matrix}{\alpha_{n - 1} = \quad \left\lfloor {\frac{\beta}{2} + \lambda + 0.5} \right\rfloor} \\{\cong \quad \left\lfloor {\frac{\beta}{2} + \frac{\beta}{2} + {0.03556n} - \frac{\beta}{n} - 0.07112 + 0.5} \right\rfloor} \\{= \quad {\beta + \left\lfloor {{- \frac{\beta}{n}} + {0.03556n} + 0.42888} \right\rfloor}}\end{matrix} & \text{(equation~~7)}\end{matrix}$

[0094] In the frequently used number of n (4˜16),$\left\lbrack {{- \frac{\beta}{n}} + {0.03556n} + 0.42888} \right\rbrack$

[0095] can be −1, 0 or +1, depends on the input. Table 2 shows thedistribution of the probability of α_(n−1)=β−1, β or β+1, where n is thebit number of a multiplicator and a multiplicand. This invention revealsthat, the greater the value of n, the closer will α_(n−1), approximateβ. For this reason, this invention can deduce a new compensation vectorsignal α_(n−1)=β. The deduction process and the concept of the wholemethod remain the same, whether p is equal to n or not. In the case ofm×n to m+n−p, the operation of product and the value of compensationvector (a dotted line, 602) are as shown in FIG. 6.

[0096] It is quite easy to fulfill this innovative compensation signal.FIG. 8 shows an conventional Array multiplier of a 5×5 multiplier; andthe dotted line in FIG. 8 indicates the operation to be removed by thisinvention. The dotted line (703) in FIG. 9 encloses the circuit for theintended compensation vector of this invention. Adding this compensationvector to the non-truncated portion will give rise to a new arraystructure, also known as reduced-width Array multiplier. The merit ofthis structure is that, no other circuits are required to implement thecompensation signal. FIG. 10 illustrates the method proposed by Jou, J.M. et al, in which an extra vertical column consists of AND-OR (AO) andAND gate circuit is added. The Array multiplier depicted in FIG. 6 andFIG. 8 applies to the number system with Sign/Un-sign Magnitude. Similarstructure is found in the Array multiplieroperated under the two'scomplement system.

[0097] Take the 8×8 to 10 (P=6) multiplier, which is depicted in FIG.11, as an example to illustrate the result of the operation of the knownfour methods and our invention. As shown in FIG. 11, a 8×8 will generateeight rows of numbers. However, for the purpose of simplicity, thenumber of rows is reduced to five, by setting the first four numbers ofa multiplicator or a multiplicand as 0. As a result, product (801)represents the product of a complete multiplication; product 2 (802) isresulted from method 1, i.e. round-off; product 3 (803) is the resultsof method 2, i.e. truncation followed by computation; product 4 (804)arises from method 3, i.e. compensation with fixed value; product 5(805) is a result of method 4, i.e. compensation with adaptive value;while product 6 (806) is created with this invention. Adding the valueof PD_((p−1)) to PD_(p) is exactly what is done by the compensatingcircuit described in this invention.

[0098]FIG. 12 illustrates the 8×8 Booth multiplication under theoperation of two's complement system. We use it to explain the usage ofthis innovative invention and the application of its compensation signalin Booth multiplier. The coder (901) and the scaler (902) operate in away similar to the way they work in conventional Booth multiplier. FIG.13 shows the summand processing unit of the 8×8 Booth multiplier. FIG.14 depicts the reduced-width low-error 8×8 to 8 Booth multiplierdescribed in this invention. The result of the simulation performed inFIG. 9 and FIG. 14 will be discussed in details in the followingsection. In fact, after being processed by a coder (901), Booth canreduce the amount of numbers for addition from. 8 to. 4. The principleof the mechanism of its summand processing unit is similar to that ofthe traditional multiplication as shown in FIG. 1.

Evaluation of Performance

[0099] Table 3 contains an evaluation of the errors of the reduced-widthlow-error Array multiplier and that presented by Jou, J. M. et al in1999. As illustrated in Table 3, when the multiplicand and themultiplicator of a multiplier is 4, 6, 8, 10, 12, 14 or 16, theevaluation of all the possible input signals for average error(ε_(ave)), the maximum error (ε_(max)) and the signal-to-noise ratio(SNR) is performed in the way as follows:${ɛ_{ave}(\%)} = {\begin{matrix}{average\_ error} \\{2^{2n} - 1}\end{matrix} \times 100\%}$ ${ɛ_{\max}(\%)} = {\begin{matrix}{max\_ error} \\{2^{2n} - 1}\end{matrix} \times 100\%}$${{SNR}({dB})} = {10\quad \log \begin{Bmatrix}{E\left\lbrack \left( {{real}\quad {product}\quad {term}} \right)^{2} \right\rbrack} \\{E\left\{ \left\lbrack {{{real}\quad {product}} - {{the}\quad {product}\quad {of}\quad {this}\quad {invention}}} \right\rbrack^{2} \right\}}\end{Bmatrix}}$

[0100] where max_error denotes the maximum error between the realproduct and the product of this invention for all input. average_erroris calculated by the following equation$\left( {{\sum\limits_{i = o}^{2^{2n}}{{real}\quad {product}}} - {{the}\quad {product}\quad {of}\quad {this}\quad {invention}}} \right)/{2^{2n}.}$

[0101] The average error, maximum error and signal-to-noise ratio ofthis invention are all better than the results of Jou, J. M. et al. Asalso explained in the report of Jou, J. M. et al., their results arebetter than the results obtained by other methods. Hence, theperformance of this method surpasses that of any known method. As far asspeed and the complexity of circuit are concerned, this invention usesone column of AND-OR(AO) less than that of Jou, J. M. et al. Thus thisinvetion has smaller area and faster operation speed.

[0102] We implement the 16×16 to 16 reduced-width Array multiplier byusing the standard cell library provided by Avant! Cooperation. Theresults show that the SNR is 90.55 dB, and the number of logical gatesis reduced by 48% as compared to the conventional Array multiplier.

[0103] Table 4 shows a comparison of the operation of n×n to n Boothmultiplier when a multiplicator and a multiplicand is 4, 6, 8, 10, 12,14 or 16 respectively. The architecture used in the reduced-width Boothmultiplier is like that shown in FIG. 14 and FIG. 16 shows the detailedcircuit for the operation of summand.

[0104] In Table 4, the left hand side shows the data of this invention.The data on the right hand side of Table 4 is the results of (n+1)method. In this method, one more column ((n−1)th) of bits in the summandis taken like that shown in FIG. 15 for 8×8 to 9 case. The detail arraystructure for the operation of summand is shown in FIG. 17.

[0105] According to Table 4, there is an increase of 3 dB (n>8) and a 8%reduction of logical gate number in this method as compared to theresult of (n+1) method in the instance of 16×16 to 16.

[0106] The improvement is even more striking, i.e. a 46% reduction oflogical gate number, and a SNR of 76.64 dB, as compared to the result ofthe original Booth multiplier. Therefore, the design of the multiplierin this invention is excellent.

[0107] To sum up, the Invention has the features of creativity, noveltyand innovativity. Although the Invention uses just a few betterpreparation examples disclosed as above, its application will not belimited to them. Anyone who is familiar with the said technique is ableto amend and/or apply the said technique partially or totally withoutgoing beyond the invention's spirit and coverage. Thus, the protectioncoverage of the invention is determined by the descriptions stated inthe application of patents. TABLE 1 The coding method of Boothmultiplier Y_(j+1) Y_(j) Y_(j−1) Action 0 0 0 No 0 0 1 Add tomultiplicand 0 1 0 Add to multiplicand 0 1 1 Add to 2×multiplicand 1 0 0Subtract from 2×multiplicand 1 0 1 Subtract from multiplicand 1 1 0Subtract from multiplicand 1 1 1 No

[0108] TABLE 2 The probability distribution curve of α_(n−1) = β−1, β orβ+1, with different bit numbers (n) α_(n−1) n β−1 β β+1 Average 45.078E−2 9.496E−1 0 β−0.050 6 3.760E−2 9.624E−1 0 β−0.038 8 4.227E−39.958E−1 0 β−0.004 10 4.158E−4 9.956E−1 0 β−4.0E−3 12 2.205E−6 1 0β−2.2E−6 14 1.602E−7 1 0 β−1.6E−7 16 2.328E−10 1 0 β

[0109] TABLE 3 Evaluation of the performance of Array multiplier∈_(ave)( %) ∈_(max ( %)) SNR (dB) this Jou, J. M. this Jou, J. M. thisJou, J. M. N invention et al. invention et al. invention et al. 42.03E−2 2.83e−2 3.34e−2 8.23e−2 21.33 18.75 6 5.89e−3 9.10e−3 2.17e−22.61e−2 32.95 29.65 8 1.62e−3 2.60e−3 6.73e−3 7.86e−3 41.96 38.40 104.35e−4 7.03e−4 2.01e−3 2.29e−3 55.80 52.20 12 1.14e−4 1.80e−4 5.83e−46.54e−4 67.41 63.31 14 4.28e−5 6.01e−5 1.62e−4 2.15e−4 78.22 75.13 169.10e−6 2.48e−5 5.15e−5 5.49e−5 90.55 87.60

[0110] TABLE 4 Evaluation of the performance of Booth multiplier ∈_(ave)(%) ∈_(max) (%) SNR (dB) this this this N invention (N+1)bits invention(N+1)bits invention (N+1)bits 4 1.83E−02 1.36E−02 5.86E−02 4.30E−021.11E+01 1.32E+01 6 5.67E−03 6.22E−03 2.08E−02 1.83E−02 2.14E+012.10E+01 8 1.63E−03 2.28E−03 6.76E−03 6.52E−03 3.22E+01 3.02E+01 104.55E−04 7.52E−04 2.08E−03 2.12E−03 4.33E+01 4.00E+01 12 1.24E−042.34E−04 6.18E−04 6.51E−04 5.35E+01 5.04E+01 14 3.29E−06 6.68E−051.79E−04 1.93E−04 6.40E+01 6.13E+01 16 8.72E−08 1.91E−05 5.18E−055.74E−05 7.66E+01 7.30E+01

What is claimed is:
 1. The Reduced-Width Low-Error Multiplier method,wherein makes proper compensation in accordance with the values of amultiplicator and a multiplicand. If a multiplicand X, has a bit lengthof m and is denoted by X_(m-1) . . . X₁ . . . X0, and a multiplicator Y,has a bit length of n and is denoted by Y_(n−1) . . . Y_(j) . . . Y0,then the product term PD, will have (m+n−p) bits and is denoted byPD_(m+n−1) . . . PD_(n) . . . PD_(p). i is the ith bit of a multiplicandX, while j is the jth bit of a multiplicator Y; The compensation signalis β, which is the sum of x_(i)y_(j) when i+j=p−1.$\beta = {{\sum\limits_{{i + j} = {p - 1}}{x_{i}y_{j}}} = {{x_{p - 1}y_{0}} + {x_{p - 2}y_{1}} + \ldots \quad + {x_{1}y_{p - 2}} + {x_{0}y_{p - 1}}}}$

And, p is the bit length of the product term to be removed. Areduced-width low-error multiplication operation can be created, byadding the value of β directly to the vertical column at the end of theright hand side of the reserved summand.
 2. A Reduced-Width Low-ErrorMultiplier method as claimed in claim 1, wherein reduces the hardwarerequired for operation and also speeds up the operation, by directlyremoving the operation of product terms of lower bits. The amplitude ofthe compensation signal varies with the multiplicator and themultiplicand. The bit length (p) of the product term intended to betruncated is changeable. The bit length (p) of product terms to betruncated may vary, and it requires no new structural design.
 3. AReduced-Width Low-Error Multiplier method as claimed in claim 1, whereinthe compensation vector is added to the preceding row, according to thedirection of the arrow.
 4. The Reduced-Width Low-Error Array Multiplier,which includes Full-Adder, Half-Adder array, AND gate and a compensatingcircuit. Full-Adder takes three input bits of the same weight adgenerates a sum and carry bits. Half-Adder takes two input bits of thesame weight ad generates a sum and carry bits. AND gates are used togenerate x_(i)y_(j). The compensation signal is β, which is the sum ofx_(i)y_(j) when i+j=p−1.$\beta = {{\sum\limits_{{i + j} = {p - 1}}{x_{i}y_{j}}} = {{x_{p - 1}y_{0}} + {x_{p - 2}y_{1}} + \ldots \quad + {x_{1}y_{p - 2}} + {x_{0}y_{p - 1}}}}$

A new Array structure, or to be precise, a reduced-with Arraymultiplier, can be created by adding the compensation vector to one ofinput of Full-Adder at the end of the right hand side of the reservedsummand.
 5. A Reduced-Width Low-Error Array Multiplier as claimed inclaim 4, no other circuits are required to implement the compensationvector.
 6. A Reduced-Width Low-Error Booth Multiplier, wherein includesBooth coder, a scaler and Full-Adder, Half-Adder array, and acompensation circuit. It is characterized by the coding of Booth Coder,the transposition with a scaler, and complements. The coding reduces thenumber of addition rows by 50%. In Full-Adder, the addition of three bitnumbers with the same category weight results in a bit of a carry and asum. In Half-Adder, adding up two bit numbers with the same categoryweight will yield a carry and a sum. The compensation signal is β, whichis the bit of the (p−1) the vertical column of the original summand.Full-Adder and Half-Adder Array work together to add up the values ofthe addition rows. The compensation vector is added to one of input ofFull-Adder at the end of the right hand side of the reserved summand. 7.A Reduced-Width Low-Error Booth Multiplier as claimed in claim 6, noother circuits are required to implement the compensation vector.